? semiconductor components industries, llc, 2007 december, 2007 - rev. 0 1 publication order number: NB4N1158/d NB4N1158 link replicator for fibre channel, gigabit ethernet, hdtv and sata up to 1.5 gb/s description the NB4N1158 is a high performance 3.3 v serial link replicator which provides the function of serial loop replication and serial loopback control commonly required in fibre channel, gbe, hdtv and sata applications. other popular applications include host bus adaptors for routing between internal and external connectors, and hot-pluggable links between redundant switch fabric cards. in is sent to both out0 and out1; each output is enabled by oe0 and oe1 when high. out0 can select either in or in1 via the mux0 pin. likewise, out1 can select between in or in0 via the mux1 pin. out can select between in0 and in1. in link replicator applications, such as the line card to switch card links, in is transmitted to both out0 and out1 which either in0 or in1 is selected at out. in host adapter applications, in goes to out0 (an internal connector) which returns data on in0. in0 is looped to out1 (an external connector) which returns data on in1 and then back to the serdes on out. the NB4N1158 is packaged in a 4.7 mm x 9.7 mm tssop-28. features ? replicates fibre channel, gigabit ethernet, hdtv, and serial ata (sata) links ? t11 fibre channel complaint at 1.0625 gb/s ? differential lvpecl outputs, external load/termination resistors required ? ieee802.3z gigabit ethernet compliant at 1.25 gb/s ? smpte-292m compliant at 1.485 gb/s ? 330 mw maximum power dissipation ? operating range: v cc = 3.135 v to 3.465 v ? 28-pin, 4.4 mm x 9.7 mm tssop package ? these are pb-free devices marking diagram* 28 lead tssop dt suffix case 948a http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information a = assembly location l = wafer lot y = year w = work week g or = pb-free package (note: microdot may be in either location) nb4n 1158 alyw figure 1. simplified application tx rx loop0 loop1 NB4N1158
NB4N1158 http://onsemi.com 2 typical applications circuit figure 2. simplified block diagram 0 1 out+ out- mux in+ in- out1+ out1- mux1 oe1 in1+ in1- mux0 out0+ out0- oe0 in0+ in0- 0 1 0 1 figure 3. pin diagram for tssop-28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vddp0 oe0 mux gnd in+ in- gnd oe1 vdd vddp out+ out- vddp gnd out0+ out0- vddp0 gnd in0+ in0- vddp1 out1+ out1- vddp1 in1+ in1- mux0 mux1 NB4N1158 table 1. oe, output enable function oex* function 1 outputs enabled 0 outputs disabled outn+ = h, outn- = h *defaults to high when left open table 2. pin description pin name i/o description 5, 6 24, 23 18, 17 in+, in- in0+, in0- in1+, in1- lvpecl input lvpecl input lvpecl input non-inverted, inverted, differential data inputs internally biased to approximately 1.2 v. 11, 12 28, 27 21, 20 out+, out- out0+, out0- out1+, out1- lvpecl output lvpecl output lvpecl output non-inverted, inverted differential outputs. typically terminated with 50 resistor to v cc - 2.0 v. 2 8 oe0 oe1 lvttl input lvttl input oe0/oe1 enables out0/out1 when high. when low, outx are powered down and both out+ and out- float high. 3 mux lvttl input selects source for out, selects either in0 (low) or in1 (high); defaults high when left open. 15 mux1 lvttl input selects source for out1. selects either in (high) or in0 (low); defaults high when left open. 16 mux0 lvttl input selects source for out0. selects either in (low) or in1 (high); defaults high when left open. 9 vdd power supply 3.3 v positive supply voltage for digital logic. 10, 13 1, 26 19, 22 vddp vddp0 vddp1 power supply 3.3 v supply for lvpecl output drivers. vddp is for out, vddp0 is for out0, and vddp1 is for out1. 4, 7, 14, 25 gnd power supply negative supply voltage, connected to ground all vdd, vddpx and gnd pins must be externally connected to appropriate power supply to guarantee proper operation.
NB4N1158 http://onsemi.com 3 table 3. attributes characteristics value internal input pullup resistor 96 k esd protection human body model machine model > 1 kv > 100 v moisture sensitivity (note 1) level 3 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 268 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 min max unit v dd positive power supply gnd = 0 v 0.5 4.0 v v inp input voltage, pecl gnd = 0 v -0.5 v dd + 0.5 v v int input voltage, ttl gnd = 0 v -0.5 v dd + 0.5 v i out output high current, pecl -50 +50 ma t c case temperature under bias -55 +125 c ta operating temperature range -40 +85 c t stg storage temperature range -65 +150 c ja thermal resistance (junction-to-ambient) 0 lfpm 500 lfpm tssop-28 76 60 c/w c/w jc thermal resistance (junction-to-case) (note 2) tssop-28 25 c/w t sol wave solder pb-free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. jedec standard multilayer board - 2s2p (2 signal, 2 power).
NB4N1158 http://onsemi.com 4 table 5. dc characteristics v dd = 3.30 v 5%, gnd = 0 v; t a = -40 c to +85 c (note 3) symbol characteristic min typ max unit v dd power supply voltage, 3.30 v 5% 3.14 3.47 v i dd power supply current (outputs open) 57 75 ma p d power dissipation; outputs open; v dd = v ddmax 330 mw v in receiver differential voltage amplitude; (in, in0, in1), ac-coupled, internally biased to 1.2 v; differential measurement - (v inn+ - v inn- ) 300 2600 mv v out50 output differential voltage swing, peak-peak; (out, out0, out1) outputs loaded / terminated with 50 to v dd C 2.0 v differential measurement - (v outn+ - v outn- ) 1000 1600 2200 mv v out75 output differential voltage swing, peak-peak; (out, out0, out1) outputs loaded / terminated with 75 to v dd C 2.0 v differential measurement - (v outn+ - v outn- ) 1200 1650 2200 mv lvcmos/lvttl inputs v ih input high voltage, ttl 2.0 v dd + 0.5 v v il input low voltage, ttl 0 0.8 v i ih input high current, ttl; v in = 2.4 v 100 a i il input low current, ttl; v in = 0.5 v -100 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. lvpecl outputs loaded with external 50 termination resistors to v tt = v dd - 2.0 v for proper operation (see figure 6). table 6. ac characteristics v dd = 3.3 v 5%, gnd = 0 v -40 c to +85 c symbol characteristic min typ max unit f in / out input / output frequency range 1.0 1.5 gb/s tr/tf output rise and fall times (note 4) 110 150 ps t pd propagation delay, in to out 0.375 4.0 ns t dj deterministic jitter added to serial input up to 1.5 gb/s; k28.5 pattern 40 ps pk-pk note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measured 20% to 80% figure 4. timing waveforms in1+/- out+/- in0+/- in+/- out0+/- out1+/- t pd t pd t j
NB4N1158 http://onsemi.com 5 figure 5. NB4N1158 application interface example NB4N1158 NB4N1158 serdes serdes tx+ tx- rx+ rx- o1+ o1- i1+ i1- i+ i- o+ o- o+ o- i+ i- i1+ i1- o1+ o1- rx+ rx- tx+ tx- 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f r r rt r r r r r r r r r r rt rt rt rt rt r is 150 for both 100 differential or 150 differential traces. rt matches the differential impedance of the link. in+/in- input functionality the differential inputs are internally biased to 1.2 v. in a typical application, the differential inputs are capacitor-coupled and will swing symmetrically above and below 1.2 v, preserving a 50% duty cycle to the outputs. with this technique, the NB4N1158 will accept any differential input allowi ng for lvpecl, cml, lvds, and hstl input levels. out+ / out- outputs the differential output buffers of the NB4N1158 utilize standard positive emitter coupled logic (pecl) architecture for out+ and out-. the outputs are designed to drive dif ferential transmission lines with nominally 50 or 75 characteristic impedance. external dc load/termination with a 50 resistor to v tt = v dd - 2.0 v is required. see figure 6 for output termination scheme. oex output enable the NB4N1158 incorporates output enable pins, oe0 and oe1, that work by powering down the output buffer and associated driving circuitry. using this approach results in both dif ferential outputs going high, and a reduction in i dd current of approx. 29 ma for each disabled output pair. when oex is low, outputs are disabled, outx+ and outx- are set high. power supply bypass information a clean power supply will optimize the performance of the device. the nb4 n1158 provides separate power supply pins for the digital circuitry (v dd ) and lvpecl outputs (vddpn). placing a bypass capacitor of 0.01 f to 0.1 f on each vdd pin will help ensure a noise free v dd power supply. the purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive digital core logic. figure 6. typical termination for output driver and device evaluation (see application note and8020/d - termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc - 2.0 v
NB4N1158 http://onsemi.com 6 resource reference of application notes and8002 - marking and date codes and8009 - eclinps plus spice i/o model kit and8020 - termination of ecl logic devices ordering information device package shipping ? NB4N1158dtg tssop-28 (pb-free) 50 units / rail NB4N1158dtr2g tssop-28 (pb-free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB4N1158 http://onsemi.com 7 package dimensions ????? ????? 0.20 a e ??? ??? 0.25 15 28 14 pin one location notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. b e e1 b c 1 0.10 seating a c d c plane 0.05 a a2 a1 b 28x 0.10 a b c a a detail a dim min max millimeters a --- 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 d 9.60 9.80 e 6.40 bsc e1 4.30 4.50 e 0.65 bsc l 0.45 0.75 l1 1.00 ref r 0.09 --- r1 0.09 --- s 0.20 --- 01 0 8 02 12 ref 03 12 ref l 03 01 r r1 s 02 h gauge plane (b) b1 c1 c 2x 28 lead tssop dt suffix case 948aa-01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 NB4N1158/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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